Intel touts Knights Corner 1 teraflop performance
New accelerator chip based om Many Integrated Core architecture breaks the one-teraflop barrier
Intel yesterday showed off its first commercial co-processor to break the one-teraflop (TFLOP), or one trillion calculations per second, performance barrier.
Its Knights Corner accelerator chip, based on the Intel Many Integrated Core (Intel MIC) architecture, demonstrated its 1 TFLOP performance running on a test two-socket Xeon server at the Supercomputing conference in Seattle.
Intel said the exhibit reiterated its commitment to delivering efficient and programming-friendly platforms for highly parallel applications in high-performance computing (HPC) tasks, such as weather modelling, tomography and advanced materials simulation.
Having this performance now in a single chip based on Intel MIC architecture is a milestone that will once again be etched into HPC history.
Rajeeb Hazra, Intel general manager of technical computing and its connected systems group, said the first demonstration of a Teraflop supercomputer was in 1997 and used 9,680 Intel Pentium Pro processors as part of Sandia Lab's "ASCI RED" system at a cost of $55 million (34.9m).
"Having this performance now in a single chip based on Intel MIC architecture is a milestone that will once again be etched into HPC history," he said.
The chipmaker said Knights Corner will be manufactured using its 3D Tri-Gate 22nm transistor process and feature more than 50 cores. It did not, however, offer any more detailed specifications.
Hazra added that the Knights Corner chip could be accessed and programmed as though it were a functional HPC compute node, unlike traditional graphic processing unit (GPUs) accelerators.
This enables it to be visible to applications as though it were a computer running its own Linux-based operating system (OS) independent of the host OS.
Targeting highly parallel processing workloads and existing x86 programming models and tools, its new performance level was measured using the Double-precision, General Matrix-Matrix multiplication (DGEMM) benchmark.
The Intel MIC architecture is designed to eliminate the need to port the code to a new programming environment in order to run existing applications.
This capability will allow scientists to use both CPU and co-processor performance simultaneously with existing x86-based applications, saving time, cost and resources that would otherwise be needed to rewrite them to alternative proprietary GPU languages, according to Intel.
The chipmaker said it already had a customer for a 10-petaflop system running its Knights Corner co-processor on PCI-Express processor slots, which will begin installation next year. The system, for the Texas Advanced Computing Centre, is expected to become fully operational in 2013.
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