Intel unveils new transistor tech for Tiger Lake

Intel has unveiled what's next for the chip maker at its Architecture Day 2020, revealing a glimpse at the Tiger Lake platform, Willow Cove architecture and a new transistor technology.

That is the 10nm SuperFin, which Intel says is a redefinition of its FinFET (fin field-effect transistor). "After years of refining the FinFET transistor, Intel is redefining the technology to enable the largest single intranode enhancement in its history, delivering performance improvement comparable to a full-node transition," the company said in a statement.

The SuperFin technology will allow more current through the channel by increasing strain and reducing resistance, improve the gate process and provide an additional gate pitch, and use a new material arranged in super thin lattice to dramatically increase capacitance in the same footprint.

And all that means a serious leap forward in performance, despite staying with the 10nm process after delaying 7nm until 2022. "It is 20%, the largest intra-node jump ever in our history,” Raja Koduri, Intel’s chief architect, said of the performance gain in an interview with Reuters. “It’s actually [the] same as what you would get with one full Moore’s Law node of performance.”

That system will be first seen in the Tiger Lake chips due this autumn, which will use the Willow Cove CPU architecture alongside the new 10nm SuperFin technology and Xe graphics. Intel claimed Tiger Lake will offer more processing power while drawing less power.

"We unpacked details of the upcoming Tiger Lake system-on-chip architecture, which provides a generational leap in CPU performance, leadership graphics, leadership artificial intelligence (AI), more memory bandwidth, additional security features, better display, better video and more," said Raja Koduri, senior vice president, chief architect, and general manager of Architecture, Graphics, and Software at Intel.

That will also see the arrival of Intel's Xe-LP graphics. "Xe-LP powers leadership graphics in Tiger Lake and is our most efficient microarchitecture for PC and mobile computing platforms," Koduri said. "Xe-LP also powers our first discrete GPU in more than 20 years, codenamed DG1. This GPU is now in production."

He added: "We also introduced the first Intel server GPU, powered by Xe-LP. This GPU will ship later this year and deliver class-leading stream density and visual quality for media transcode and streaming."

Alongside that, Intel said its first Xe-HP chip is now being sampled by datacentre customers. "Xe-HP is the industry’s first multi tiled, highly scalable, high-performance GPU architecture, providing petaflop-scale AI performance and rack-level media performance in a single package based on our EMIB technology. Xe-HP will leverage enhanced SuperFin technology," says Koduri.

More details about Intel's Tiger Lake are expected to be revealed at a further event in September.