Intel partners with DARPA to build 'state-of-the-art' security chips

The corner of a CPU chip seen on a circuit board
(Image credit: Shutterstock)

Intel will develop customised chips embedded with novel hardware-based security protections as part of a three-year partnership with the R&D wing of the US Department of Defense (DoD).

Dubbed SAHARA, the chipmaker's agreement with the US Defense Advanced Research Projects Agency (DARPA) will see it develop a specialised version of its Application-Specific Integrated Circuits (ASICs).

The ultimate goal is to manufacture advanced 10nm chips with integrated, state-of-the-art cyber protections that can be fitted into DoD systems as well as other commercial devices.

DARPA aims to transform the ASIC chips currently in use in DoD systems, as well as develop new iterations that it can deploy in future with significantly higher performance and lower power consumption.

The agreement comes only a week after Intel struck a separate partnership with DARPA to develop a next-gen form of encryption, known as fully homomorphic encryption (FHE).

“SAHARA aims to dramatically shorten the ASIC design process through automation while adding unique security features to support manufacturing of the resulting silicon in zero-trust environments,” said program manager in DARPA’s Microsystems Technology Office, Serge Leef. “Additionally, Intel will establish domestic manufacturing capabilities for the structured ASICs on their 10nm process.”

ASICs are silicon chips designed for a specific purpose, created to perform a repeated function highly effectively. This is opposed to general-purpose CPUs which can perform a variety of functions but with much less efficiency. Once built, they cannot be reprogrammed or reconfigured to perform another function, unlike Field-Programmable Gate Arrays (FPGAs), which keeps manufacturing costs low for mass production.

Intel will develop unique cyber security safeguards for these custom ASICs to enhance the level of in-built data protection, and prevent intellectual property from being counterfeited or reverse-engineered.

Research teams based at the University of Florida, Texas A&M, and the University of Maryland will use verification, validation, and a variety of attack methods to test the specific security measures before they’re integrated into the ASIC design. Intel will then use its ASIC technology to develop platforms that speed up development time and reduce engineering costs when compared with traditional methods for building ASICs.

Keumars Afifi-Sabet
Features Editor

Keumars Afifi-Sabet is the Features Editor for ITPro, CloudPro and ChannelPro. He oversees the commissioning and publication of in-depth and long-form features across all three sites, including opinion articles and case studies. He also occasionally contributes his thoughts to the IT Pro Podcast, and writes content for the Business Briefing. Keumars joined IT Pro as a staff writer in April 2018. He specialises in the public sector but writes across a breadth of core topics including cyber security and cloud computing.